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NXP Semiconductors /MIMXRT1011 /IOMUXC_SNVS_GPR /GPR3

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Interpret as GPR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPSR_MODE_ENABLE)LPSR_MODE_ENABLE 0 (DCDC_STATUS_CAPT_CLR)DCDC_STATUS_CAPT_CLR 0POR_PULL_TYPE 0 (DCDC_IN_LOW_VOL)DCDC_IN_LOW_VOL 0 (DCDC_OVER_CUR)DCDC_OVER_CUR 0 (DCDC_OVER_VOL)DCDC_OVER_VOL 0 (DCDC_STS_DC_OK)DCDC_STS_DC_OK

Description

GPR3 General Purpose Register

Fields

LPSR_MODE_ENABLE

Set to enable LPSR mode.
DCDC_STATUS_CAPT_CLR

DCDC captured status clear
POR_PULL_TYPE

POR_B pad control
DCDC_IN_LOW_VOL

DCDC_IN low voltage detect.
DCDC_OVER_CUR

DCDC output over current alert
DCDC_OVER_VOL

DCDC output over voltage alert
DCDC_STS_DC_OK

DCDC status OK

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data